Welcome

Welcome to my personal website! This site is most likely up-to-date, and I am excited to share my journey and work with you.

Feel free to explore the sections on the left to learn more about my research, publications, and blog posts. You can also download my CV to see my professional background.

Research

Interests

I am interested in:

one word: tech
broadly: Hardware Acceleration
Goal: develop energy-efficient and resource-efficient systems that are deterministic and low-latency

I am working towards contributions primarily in Hardware Acceleration and Digital Design.

Broad Scope

I aim to work with:

HLS (High-level Synthesis)
HDLs such as Verilog/SystemVerilog
frameworks for generating hardware accelerators : FINN, hls4ml or one I can hopefully build myself!
Software-Hardware Co-design
Parallel Architecture

to build systems that can be deployed on hardware for various tasks such as:

machine learning on the edge
Domain-specific accelerators (GNNs and CNNs among other DNN architectures)
classical simulation of Quantum Computers
deterministic control of mission-critical systems

Ongoing Work

Classical Simulation of multi-qubit Quantum Computation systems
Cascaded Early exit classifier with DPR
rv32i on FPGA

Publications

It's still a land of vast emptiness and placeholders, which means there's so much meaningful work to fill it up with!

Posters & Talks

Sajid, A. A., Ahmed, M.U., Islam, S., ”FPGA Based CNN Accelerator Design for low-power devices”. Poster accepted at the Bangladesh AI, Electronics, and Robotics (BEAR) Summit & National Semiconductor Symposium, Dhaka, Bangladesh. (July, 2025)